參數(shù)資料
型號: GT-48212
廠商: Galileo Technology Services, LLC
英文描述: Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器)
中文描述: 先進的交換式以太網(wǎng)控制器的10 10/100 BaseX(高級交換式10 10/100 BaseX以太網(wǎng)控制器)
文件頁數(shù): 55/135頁
文件大?。?/td> 1619K
代理商: GT-48212
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
--
DO
NOT
REPRODUCE
26
Revision 1.2
6.
MAC ADDRESS TABLE
The GT-482xx’s Address Table resides in the local DRAM array. Table 5 and Table 6 show the Address Table
structure. The Address Table structure occupies approximately 320Kbytes (in 4Mbyte configuration) or 80Kbtytes
in 1Mbyte configuration) and is entirely controlled and initialized by the GT-482xx. Following RESET, the GT-
482xx initializes the Address Table by invalidating all entries.
Modifications to the Address Table are normally made through New_Address message requests by the CPU. The
Address Table can be accessed directly, however, this mode is not recommended. Contact Galileo Technology if
your application requires direct Address Table access.
6.1
Forwarding Mask
The Forwarding Mask (forw<14:0>) controls forwarding options in managed systems. Each bit in the mask corre-
sponds to a specific port in the GT-482xx device. Port 0 corresponds to bit 0 (least significant bit), Port 13 corre-
sponds to bit 13. Bit 14 corresponds to the CPU port (if present). When the GT-482xx performs new address
learning, the forw[14:0] bits are set to 0x7FFF (all 1's).
The forw<14:0> operation is described in Table 6.
6.2
Port Number
The Port Number field in the Address Table corresponds to the port on which a specific address was detected
(learned). Port 0 = 0x0 in this field, CPU port (port 14) corresponds to 0xE.
Table 5:
Address Table Entry Format
f o r w <14: 0>
M A C < 47 :0 >
I s
I d
m ul
st
por t
#P s
P d
A
S k
V
15
48
11
1
4
11111
Number of bits in each field is shown above.
Table 6:
Address Table Entry Field Description
Bit
General Description
V
Valid - Indicates that the entry is valid
1 - Valid
0 - Not Valid
Sk
Skip - Skip this entry. It is being used to delete an entry
1 - Skip this entry
0 - Don’t skip this entry
A
Aging - This bit is used in the address aging process.
- Cleared by the GT-482xx upon receiving a packet from this station.
- Set by the GT-482xx during aging processing
(For more information see the Aging algorithm in Section 6.7)
Pd
Destination address effect on priority.
1 - enqueue to high priority queue.
相關PDF資料
PDF描述
GT-64010A System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統(tǒng)控制器)
GT-64012 Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級高速緩存控制器)
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級通信協(xié)議(以太網(wǎng)、快速以太網(wǎng)、HDLC)控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
相關代理商/技術參數(shù)
參數(shù)描述
GT48212-A6-PBB1C000 制造商:Marvell 功能描述:
GT48212-A6-PBB-C000 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays
GT48300-A1-BBE1C083 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083
GT48300-A1-BBE-C000 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000
GT48300-A1-BBE-C08 制造商:Marvell 功能描述:MVLGT48300-A1-BBE-C083 4 PORT 83MHZ G.LI