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參數(shù)資料
| 型號： | GT-48212 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| 中文描述： | 先進的交換式以太網(wǎng)控制器的10 10/100 BaseX（高級交換式10 10/100 BaseX以太網(wǎng)控制器） |
| 文件頁數(shù)： | 73/135頁 |
| 文件大?。?/td> | 1619K |
| 代理商： | GT-48212 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
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DO
NOT
REPRODUCE
42
Revision 1.2
Each port holds its own Source Address for flow control packets. The Source Address consists of 44 common bits
for all ports and four dedicated bits per port. The common bits (47:4) are held in the Source Address High and Low
registers. The four least significant bits are held in the Port Control registers.
8.14
802.1q VLAN Tagging Support
The GT-482xx has the ability to receive and transmit Ethernet frames up to 1536 bytes in length, thereby accom-
modating the IEEE 802.1q standard VLAN tagging bytes. This feature is enabled/disabled by bit 13 in the Port
Control register (also sampled from DAddr[8] at RESET.) The default is to disable this feature. Bytes longer than
1536 are discarded as over-size frames.
8.15
MII Management Interface (SMI)
The GT-482xx MAC includes an MII Management Interface (SMI) for MII compliant PHY devices. This enables the
passing of control and status parameters between the GT-482xx and the PHY (parameters specified by the CPU)
by one serial pin (MDIO) and a clocking pin (MDC), and reduces the number of control pins required for PHY
mode control. Typically, the GT-482xx continuously queries the PHY devices for their link status, without CPU
intervention. The predefined PHY addresses for the link query are 1 and 2 (out of possible 32 addresses). This
protocol complies with the National DP83840 PHY device as well as other available PHYs.
A CPU connected to the GT-482xx has access to all of the PHY addresses/registers, by writing and reading to/
from a dedicated set of the GT-482xx SMI control registers. The SMI allows the CPU to have direct control over an
MII-compatible PHY device via the GT-482xx SMI control register. This allows the driver software to place the
PHY in specific modes such as Full Duplex, Loopback, Power Down, 10/100 speed selection as well as control of
the PHY device’s Auto-Negotiation function, if it exists. The CPU writes commands to the GT-482xx SMI register
and the GT-482xx reads or writes control/status parameters to the PHY device via a serial, bi-directional data pin
called MDIO. These serial data transfers are clocked by the GT-482xx MDC clock output.
The delay time between two consecutive SMI write transactions is at least (4x64=256) MDC clock cycles.
8.15.1
SMI Cycles
The SMI protocol consists of a bit stream driven or sampled by the GT-482xx on each rising edge of the MDC
clock. The bit stream format of the SMI frame is described in Table 10.
PRE (Preamble). At the beginning of each transaction, the GT-482xx sends a sequence of 32 contiguous
logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it
can use to establish synchronization.
ST (Start of Frame). A Start of Frame pattern of 01.
OP (Operation Code). 10 - Read; 01 - Write
PhyAd (PHY Address). A 5 bit address of the PHY device (32 possible addresses). The first PHY
address bit transmitted by the GT-482xx is the MSB of the address.
RegAd (Register Address). A 5 bit address of the PHY register (32 possible registers in each PHY). The
first register address bit transmitted by the GT-482xx is the MSB of the address. The GT-482xx always
queries the PHY device for status of the link by reading register 1, bit 2.
TA (Turn Around). The turnaround time is a 2 bit time spacing between the Register Address field and
the Data field of the SMI frame to avoid contention during a read transaction. During a Read transaction
the PHY should not drive MDIO in the first bit time and drive ‘0’ in the second bit time. During a write
transaction, the GT-482xx drives a ‘10’ pattern to fill the TA time.
Table 10: SMI Bit Stream Format
PR E
S T
O P
P h y Ad
Re g A d
TA
D a ta
I D L E
READ
1...1
01
10
AAAAA
RRRRR
Z0
D..D(16)
Z
WRITE
1...1
01
AAAAA
RRRRR
10
D..D(16)
Z
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