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| 型號(hào)： | HC05J5AGRS |
| 英文描述： | 68HC(7)05J5A General Release Specification |
| 中文描述： | 68HC（7）05J5A總發(fā)行規(guī)格 |
| 文件頁(yè)數(shù)： | 29/106頁(yè) |
| 文件大小： | 1366K |
| 代理商： | HC05J5AGRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INTERRUPTS
MOTOROLA
4-3
4.3
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the con-
tents of memory locations $0FFC and $0FFD.
4.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
4.5
EXTERNAL INTERRUPT (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in
Figure 4-2
.
Figure 4-2. IRQ Function Block Diagram
IRQ
LATCH
R
V
DD
IRQ Pin
PA0
IRQE
Mask Option
(IRQ Level)
IRQF
to IRQ
processing
in CPU
IRQR
to BIH & BIL
instruction
sensing
RST
Mask Option
(Port A External Int.)
PA1
PA2
PA3
IRQ Fetch Vector
IRQE1
IRQ1
LATCH
R
V
DD
IRQR1
RST
IRQF1
IRQE1
PA7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| HC05J5GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05J5 General Release Specification |
| HC05JB3GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05JB3 and 68HC705JB3 General Release Specification |
| HC05JB4GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC(7)05JB4 General Release Specification |
| HC05JJ6GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05JJ6 and 68HC05JP6 General Release Specification |
| HC05K3GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05K3 General Release Specification |
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