參數(shù)資料
型號: HC05J5AGRS
英文描述: 68HC(7)05J5A General Release Specification
中文描述: 68HC(7)05J5A總發(fā)行規(guī)格
文件頁數(shù): 69/106頁
文件大?。?/td> 1366K
代理商: HC05J5AGRS
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INSTRUCTION SET
MOTOROLA
10-1
SECTION 10
INSTRUCTION SET
This section describes the addressing modes and instruction types.
10.1 ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
Inherent
Immediate
Direct
Extended
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
Relative
10.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
10.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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