參數(shù)資料
型號(hào): HC05J5AGRS
英文描述: 68HC(7)05J5A General Release Specification
中文描述: 68HC(7)05J5A總發(fā)行規(guī)格
文件頁(yè)數(shù): 71/106頁(yè)
文件大?。?/td> 1366K
代理商: HC05J5AGRS
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
INSTRUCTION SET
MOTOROLA
10-3
10.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
10.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
10.1.9 Instruction Types
The MCU instructions fall into the following five categories:
Register/Memory Instructions
Read-Modify-Write Instructions
Jump/Branch Instructions
Bit Manipulation Instructions
Control Instructions
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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