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參數(shù)資料
| 型號： | HC05J5AGRS |
| 英文描述： | 68HC(7)05J5A General Release Specification |
| 中文描述： | 68HC（7）05J5A總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 70/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05J5AGRS |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
10-2
INSTRUCTION SET
MC68HC05J5A
REV 2.1
10.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
10.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
10.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
10.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC05J5GRS | 68HC05J5 General Release Specification |
| HC05JB3GRS | 68HC05JB3 and 68HC705JB3 General Release Specification |
| HC05JB4GRS | 68HC(7)05JB4 General Release Specification |
| HC05JJ6GRS | 68HC05JJ6 and 68HC05JP6 General Release Specification |
| HC05K3GRS | 68HC05K3 General Release Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC05J5GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05J5 General Release Specification |
| HC05JB3GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05JB3 and 68HC705JB3 General Release Specification |
| HC05JB4GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC(7)05JB4 General Release Specification |
| HC05JJ6GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05JJ6 and 68HC05JP6 General Release Specification |
| HC05K3GRS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:68HC05K3 General Release Specification |
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