參數(shù)資料
型號： HMT351V7BFR8C-H9
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： DDR DRAM MODULE, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁數(shù)： 15/61頁
文件大?。?/td> 1050K
代理商： HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
22
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Notes:
1. Vref = VrefDQ (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 34.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Single Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-800/1066
DDR3-1333
Unit Notes
Min
Max
Min
Max
VIH.CA(DC100)
DC input logic high
Vref + 0.100
VDD
Vref + 0.100
VDD
V
1
VIL.CA(DC100)
DC input logic low
VSS
Vref - 0.100
VSS
Vref - 0.100
V
1
VIH.CA(AC175)
AC input logic high
Vref + 0.175
Note2
-
V
1, 2
VIL.CA(AC175)
AC input logic low
Note2
Vref - 0.175
-
V
1, 2
VIH.CA(AC150)
AC Input logic high
Vref + 0.150
Note2
Vref + 0.150
Note2
V
1, 2
VIL.CA(AC150)
AC input logic low
Note2
Vref - 0.150
Note2
Vref - 0.150
V
1, 2
VRefDQ(DC)
Reference Voltage for DQ,
DM inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V
3, 4
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