參數(shù)資料
型號: HMT351V7BFR8C-H9
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 30/61頁
文件大?。?/td> 1050K
代理商: HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
36
Refresh parameters by device density
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Refresh parameters by device density
Parameter
RTT_Nom Setting
512Mb
1Gb
2Gb
4Gb
8Gb
Units Notes
REF command ACT or
REF command time
tRFC
90
110
160
300
350
ns
Average periodic
refresh interval
tREFI
0
°C ≤ T
CASE 85 °C
7.8
us
85
°C < T
CASE 95 °C
3.9
us
1
For specific Notes See “Speed Bin Table Notes” on page 39.
Speed Bin
DDR3-800E
Unit
Notes
CL - nRCD - nRP
6-6-6
Parameter
Symbol
min
max
Internal read command to first data
tAA
15
20
ns
ACT to internal read or write delay time
tRCD
15
ns
PRE command period
tRP
15
ns
ACT to ACT or REF command period
tRC
52.5
ns
ACT to PRE command period
tRAS
37.5
9 * tREFI
ns
CL = 5
CWL = 5
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1, 2, 3
Supported CL Settings
6
nCK
Supported CWL Settings
5
nCK
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