- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296194 > HMT351V7BFR8C-H9 (HYNIX SEMICONDUCTOR INC) DDR DRAM MODULE, DMA240 PDF資料下載
參數(shù)資料
| 型號： | HMT351V7BFR8C-H9 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 37/61頁 |
| 文件大小： | 1050K |
| 代理商： | HMT351V7BFR8C-H9 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
Rev. 0.1 / Feb. 2010
42
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
”0” and “LOW” is defined as VIN <= VILAC(max).
”1” and “HIGH” is defined as VIN >= VIHAC(max).
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HN4400 | NPN EXPITAXIAL SILICON TRANSISTOR |
| HN5400 | PNP Silicon Expitaxial Planar Transistor for general purpose, high voltage amplifier applications |
| HN5401 | PNP Silicon Expitaxial Planar Transistor for general purpose, high voltage amplifier applications |
| HN546 | NPN Silicon Epitaxial Planar Transistor |
| HN547 | NPN Silicon Epitaxial Planar Transistor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMT351V7BMR4C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR4C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7CFR4A | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR3L SDRAM VLP Registered DIMM Based on 2Gb C-die |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。