參數(shù)資料
型號: HMT351V7BFR8C-H9
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 26/61頁
文件大小: 1050K
代理商: HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
32
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output slew Rate Definition
Differential Output Slew Rate Definition
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff (AC)
VOHdiff (AC)
[VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff (AC)
VOLdiff (AC)
[VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Slew Rate
DDR3-800
DDR3-1066
DDR3-1333
Units
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Differential Output Slew Rate
SRQdiff
5
10
5
10
5
10
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Delta
TFdiff
Delta
TRdiff
vOHdiff(AC)
vOLdiff(AC)
O
Di
ff
ere
nt
ia
lOu
tp
ut
Vo
lta
ge
(i
.e.
DQS
-DQS
)
Differential Output Slew Rate Definition
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