參數(shù)資料
型號(hào): HSP43220JC-33Z
廠商: Intersil
文件頁(yè)數(shù): 12/21頁(yè)
文件大?。?/td> 0K
描述: IC DECIMATING DGTL FILTER 84PLCC
標(biāo)準(zhǔn)包裝: 15
濾波器類(lèi)型: 數(shù)字
濾波器數(shù): 4
電源電壓: 4.75 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 84-PLCC(29.21x29.21)
包裝: 管件
2
FN2486.10
October 10, 2008
Block Diagram
INPUT CLOCK
DATA INPUT
DATA OUT
FIR CLOCK
DECIMATION UP TO 1024
DECIMATION UP TO 16
DATA READY
24
CONTROL AND COEFFICIENTS
16
FIR
DECIMATION
FILTER
HIGH ORDER
DECIMATION
FILTER
Pinout
HSP43220
84 PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
Pin Description
NAME
TYPE
DESCRIPTION
VCC
The +5V power supply pins.
GND
The device ground.
CK_IN
I
Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
FIR_CK
I
Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
DATA_
IN
1
DATA_
IN
0
V
CC
GND
CK_
IN
V
CC
GND
DATA_
IN
2
DATA_
IN
3
DATA_
IN
4
DATA_
IN
5
DATA_
IN
6
DATA_
IN
7
DATA_
IN
8
DATA_
IN
9
DATA_
IN
10
DATA_
IN
11
DATA_
IN
12
DATA_
IN
13
DATA_
IN
14
DATA_
IN
15
DATA_OUT 1
DATA_OUT 0
GND
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
VCC
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
A0
C_BUS 15
A1
VCC
GND
STARTOUT
WR
CS
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
C_BUS 9
C_BUS 8
C_BUS 7
C_BUS 6
STARTIN
C_BU
S
5
C_BU
S
4
C_BU
S
3
C_BU
S
2
C_BU
S
1
C_BU
S
0
V
CC
OUT_SE
LH
OU
T
_E
N
P
OU
T
_E
N
X
GN
D
A
TA_
RDY
FIR_CK
V
CC
GN
D
DA
T
A
_O
U
T
23
DA
T
A
_O
U
T
22
DA
T
A
_O
U
T
21
DA
T
A
_O
U
T
20
DA
T
A
_O
U
T
19
DA
T
A
_O
U
T
18
RESET
ASTARTIN
HSP43220
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