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參數(shù)資料
| 型號： | HSP43220JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECIMATING DGTL FILTER 84PLCC |
| 標準包裝： | 15 |
| 濾波器類型： | 數(shù)字 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
9
FN2486.10
October 10, 2008
Start Logic
The Start Logic generates a start signal that is used
internally to synchronously start the DDF. If ASTARTIN is
asserted (STARTIN must be tied high) the Start Logic
synchronizes it to CK_IN by double latching the signal and
generating the signal STARTOUT, which is shown in Figure
8. The STARTOUT signal is then used to synchronously start
other DDFs in a multi-chip configuration (the STARTOUT
signal of the first DDF would be tied to the STARTIN of the
second DDF). The NAND gate shown in Figure 8 then
passes this synchronized signal to be used on-chip to
provide a synchronous start. Once started, the chip requires
a RESET to halt operation.
When STARTIN is asserted (ASTARTIN must be tied high)
the NAND gate passes STARTIN which is used to provide the
internal start, ISTART, for the DDF. When RESET is asserted
the internal start signal is held inactive, thus it is necessary to
assert either ASTARTIN or STARTIN in order to start the DDF.
The timing of the first valid DATA_IN with respect to
START_IN is shown in the Timing Waveforms.
In using ASTARTIN or STARTIN a high to low transition must
be detected by the rising edge of CK_IN, therefore these
signals must have been high for more than one CK_IN cycle
and then taken low.
The FIR Section
The second filter in the top level block diagram is a Finite
Impulse Response (FIR) filter which performs the final
shaping of the signal spectrum and suppresses the aliasing
components in the transition band of the HDF. This enables
the DDF to implement filters with narrow pass bands and
sharp transition bands.
The FIR is implemented in a transversal structure using a single
multiplier/accumulator (MAC) and RAM for storage of the data
and filter coefficients as shown in Figure 9. The FIR can
implement up to 512 symmetric taps and decimation up to 16.
The FIR is divided into 2 sections: the FIR filter section and
the FIR control logic.
H_Register 2 (A1 = 1, A0 = 1)
FIGURE 7.
DDF Control Registers (Continued)
RESERVED
H_GROWTH
H_STAGES
G5
G4
G3
G2
G1
G0
N2
N1
N0
H_STAGES
Bits N0-N2 are used to select the number of stages or order of the
HDF filter. The number that is programmed in is equal to the
required number of stages. For a 5th order filter, H_STAGES
would be set equal to 5.
H_GROWTH
Bits G0-G5 are used to select the proper amount of growth bits.
H_GROWTH is calculated using Equation 1:
where the CEILING { } means use the next largest integer of the
result of the value in brackets and log is the log to the base 10.
The value of H_GROWTH represents the position of the LSB on
the output of the data shifter.
H_GROWTH
50
CEILING H_STAGESx
H
DEC
()/log(2)
log
{}
–
=
(EQ. 1)
15 14 13 12 11 10
9
8
7654
3
2
1
0
FIGURE 8. START LOGIC
CK_IN
RESET
ISTART
STARTIN
STARTOUT
ASTARTIN
S
DQ
S
DQ
HSP43220
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