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參數(shù)資料
| 型號： | HSP43220JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECIMATING DGTL FILTER 84PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | 數(shù)字 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
7
FN2486.10
October 10, 2008
FC_Register (A1 = 0, A0 = 1)
FIGURE 5.
DDF Control Registers (Continued)
F_CF
C19 C18 C17 C16 C15 C14 C13 C12
C11
C10
C9
C8
C7
C6
C5
C4
XX
C3
C2
C1
C0
F_CF
Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are
required to write each coefficient which is 2's complement fractional format. The first
write loads C19 through C4; C3 through C0 are loaded on the second write cycle. As
the coefficients are written into this register they are formatted into a 20-bit coefficient
and written into the Coefficient RAM sequentially starting with address location zero.
The coefficients must be loaded sequentially, with the center tap being the last
coefficient to be loaded. See “Coefficient RAM” on page 10.
15
14
13
12
11
10
987
654321
0
HSP43220
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