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參數(shù)資料
| 型號： | HSP43220JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECIMATING DGTL FILTER 84PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | 數(shù)字 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
13
FN2486.10
October 10, 2008
Multi-Chip Start Configurations
Since there are two methods to start-up the DDF, there are also
two configurations that can be used to start-up multiple chips.
The first method is shown in Figure 12. The timing of the
STARTOUT circuitry starts the second DDF on the same
clock as the first. If more DDFs are also to be started
synchronously, STARTOUT is connected to their STARTIN's.
The second method to start-up DDFs in a multiple chip
configuration is to use the synchronous start scenario.
The STARTIN input is wired to all the chips in the chain, and is
asserted by a active low synchronous pulse that has been
externally synchronized to CK_IN. In this way all DDFs are
synchronously started. The ASTARTIN input on all the chips is
tied high to prevent false starts. The STARTOUT outputs are all
left unconnected. This configuration is illustrated in Figure 13.
Chip Set Application
The HSP43220 is ideally suited for narrow band filtering in
Communications, Instrumentation and Signal Processing
applications. The HSP43220 provides a fully integrated
solution to high order decimation filtering.
The combination of the HSP43220 and the HSP45116
(which is a NCOM Numerically Controlled Oscillator /
Modulator) provides a complete solution to digital receivers.
The diagram in Figure 14 illustrates this concept.
The HSP45116 down converts the signal of interest to
baseband, generating a real component and an imaginary
component. A HSP43220 then performs low pass filtering
and reduces the sampling rate of each of the signals.
The system scenario for the use of the DDF involves a
narrow band signal that has been over-sampled. The signal
is over-sampled in order to capture a wide frequency band
containing many narrow band signals. The NCOM is “tuned”
to the frequency of the signal of interest and performs a
complex down conversion to baseband of this signal, which
results in a complex signal centered at baseband. A pair of
DDFs then low pass filters the NCOM output, extracting the
signal of interest.
Design Trade-Off Considerations
Equation 2 in the Functional Description section expresses
the relationship between the number of TAPS which can be
implemented in the FIR as a function of CK_IN, FIR_CK,
HDEC, FDEC. Table 1 provides a tradeoff of these
parameters. For a given speed grade and the ratio of the
clocks, and assuming minimum decimation in the HDF, the
number of FIR taps that can be implemented is given in
Equation 2.
FIGURE 12. ASYNCHRONOUS START-UP
FIGURE 13. SYNCHRONOUS START-UP
DDF
ASTARTIN
STARTIN
STARTOUT
DDF
ASTARTIN
STARTOUT
CK_IN
FIR_CK
+5V
NC
STARTIN
+5V
TO OTHER DDF'S
CK_IN
FIR_CK
DDF
ASTARTIN
STARTIN
STARTOUT
DDF
ASTARTIN
STARTOUT
+5V
STARTIN
NC
CK_IN
FIR_CK
CK_IN
FIR_CK
HSP43220
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43220TM-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
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| HSP43220VC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP43220VC-33 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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