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參數(shù)資料
| 型號(hào)： | IDT82V3280DQG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 105/171頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLL WAN SE STRATUM 2 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 14:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | 82V3280DQG8 |
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IDT82V3280
WAN PLL
Functional Description
39
December 9, 2008
3.12
T0 / T4 APLL
A T0 APLL and a T4 APLL are provided for a better jitter and wander
performance of the device output clocks.
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
The input of the T0/T4 APLL can be derived from one of the T0 and
T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] /
T4_APLL_PATH[3:0] bits respectively.
Both the APLL and DPLL outputs are provided for selection for the
device output.
3.13
OUTPUT CLOCKS & FRAME SYNC SIGNALS
The device supports 9 output clocks and 2 frame sync output signals
altogether.
3.13.1
OUTPUT CLOCKS
The device provides 9 output clocks.
According to the output port technology, the output ports support the
following technologies:
AMI;
PECL/LVDS;
CMOS.
OUT1 ~ OUT5 and OUT9 output a CMOS signal.
OUT6 and OUT7 output a PECL or LVDS signal, as selected by the
OUT6_PECL_LVDS bit and the OUT7_PECL_LVDS bit respectively.
OUT8 outputs an AMI signal.
The outputs on OUT1 ~ OUT7 are variable, depending on the signals
derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the corre-
sponding OUTn_PATH_SEL[3:0] bits (1
≤ n ≤ 7). The derived signal can
be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by the
corresponding OUTn_PATH_SEL[3:0] bits (1
≤ n ≤ 7). If the signal is
derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for
the output frequency. If the signal is derived from the T0/T4 APLL output,
please refer to Table 25 for the output frequency.
The output on OUT8 is derived from T0 or T4 DPLL 77.76 MHz path,
as selected by the OUT8_PATH_SEL bit. After being divided automati-
cally, the output is of 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz, as
selected by the 400HZ_SEL bit. Its duty cycle is 50:50 or 5:8, as deter-
mined by the AMI_OUT_DUTY bit.
The output on OUT9 is derived from T0 or T4 DPLL 16E1/16T1 path,
as selected by the OUT9_PATH_SEL bit. After being divided automati-
cally, the output is of 2.048 MHz or 1.544 MHz, as selected by the
IN_SONET_SDH bit.
The outputs on OUT8 and OUT9 can be enabled or disabled, or may
be affected by the status of the T4 input clock. It is determined by the
OUT8_EN / OUT9_EN and T4_INPUT_FAIL 1 / T4_INPUT_FAIL 2 bits.
Refer to Table 26.
The outputs on OUT1 to OUT7 and OUT9 can be inverted, as deter-
mined by the corresponding OUTn_INV bit (1
≤ n ≤ 7 or n = 9).
All the output clocks derived from T0/T4 selected input clock are
aligned with the T0/T4 selected input clock respectively every 125 s
period.
Table 23: Related Bit / Register in Chapter 3.12
Bit
Register
Address (Hex)
T0_APLL_BW[1:0]
T0_T4_APLL_BW_CNFG
6A
T4_APLL_BW[1:0]
T0_APLL_PATH[3:0]
T0_DPLL_APLL_PATH_CNFG
55
T4_APLL_PATH[3:0]
T4_DPLL_APLL_PATH_CNFG
60
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT82V3280EQG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT |
| IDT82V3280EQG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3280EQGBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PF | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:WAN PLL |
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