參數資料
型號: IDT82V3280DQG8
廠商: IDT, Integrated Device Technology Inc
文件頁數: 142/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標準包裝: 750
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數: 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V3280DQG8
IDT82V3280
WAN PLL
Programming Information
72
December 9, 2008
MS_SL_CTRL_CNFG - Master Slave Control
PROTECTION_CNFG - Register Protection Mode Configuration
Address: 13H
Type: Read / Write
Default Value: XXXXXXX0
Bit
Name
Description
7-1
-
Reserved.
0
MS_SL_CTRL
These bits, together with the MS/SL pin, control whether the device is configured as the Master or as the Slave.
The default value of this bit is ‘0’.
Address: 7EH
Type: Read / Write
Default Value: 10000101
Bit
Name
Description
7 - 0
PROTECTION_DATA[7:0]
These bits select a register write protection mode.
00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register.
10000101: Fully Unprotected mode. All the writable registers can be written. (default)
10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not
including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode.
7
6543210
-
------
MS_SL_CTRL
Master/Slave Control
Result
MS/SL pin
MS_SL_CTRL Bit
High
0Master
1Slave
Low
0Slave
1Master
7654321
0
PROTECTION_
DATA7
PROTECTION_
DATA6
PROTECTION_
DATA5
PROTECTION_
DATA4
PROTECTION_
DATA3
PROTECTION_
DATA2
PROTECTION_
DATA1
PROTECTION_
DATA0
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