參數(shù)資料
型號: IDT82V3280DQG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 144/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V3280DQG8
IDT82V3280
WAN PLL
Programming Information
74
December 9, 2008
7.2.2
INTERRUPT REGISTERS
INTERRUPT_CNFG - Interrupt Configuration
INTERRUPTS1_STS - Interrupt Status 1
Address: 0CH
Type: Read / Write
Default Value: XXXXXX10
Bit
Name
Description
7 - 2
-
Reserved.
1HZ_EN
This bit determines the output characteristics of the INT_REQ pin.
0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive.
1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt
is inactive. (default)
0INT_POL
This bit determines the active level on the INT_REQ pin for an active interrupt indication.
0: Active low. (default)
1: Active high.
Address: 0DH
Type: Read / Write
Default Value: 11111111
Bit
Name
Description
7 - 0
INn
This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn; i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b7~0, 4AH). Here n is any one of 8 to 1.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
76543
21
0
---
HZ_EN
INT_POL
76
543
21
0
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
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