參數(shù)資料
型號(hào): IDT82V3280DQG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 136/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V3280DQG8
IDT82V3280
WAN PLL
Programming Information
67
December 9, 2008
NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration
Address: 06H
Type: Read / Write
Default Value: 00000000
Bit
Name
Description
7 - 0 NOMINAL_FREQ_VALUE[23:16]
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
Address: 07H
Type: Read / Write
Default Value: XXX0XXXX
Bit
Name
Description
7 - 5
-
Reserved.
4
T4_T0_SEL
A part of the registers are shared by T0 and T4 paths. These registers are addressed 26H ~ 2CH, 4EH, 4FH, 5AH, 5BH, 62H ~
64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path.
0: T0 path (default).
1: T4 path.
3 - 0
-
Reserved.
76
543
21
0
NOMINAL_FRE
Q_VALUE23
NOMINAL_FRE
Q_VALUE22
NOMINAL_FRE
Q_VALUE21
NOMINAL_FRE
Q_VALUE20
NOMINAL_FRE
Q_VALUE19
NOMINAL_FRE
Q_VALUE18
NOMINAL_FRE
Q_VALUE17
NOMINAL_FRE
Q_VALUE16
7
654
321
0
-
T4_T0_SEL
-
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