參數(shù)資料
型號(hào)： IDT82V3280DQG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 91/171頁
文件大小： 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V3280DQG8
IDT82V3280
WAN PLL
Functional Description
26
December 9, 2008
3.6.2
FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni-
toring) do not affect the input clock selection.
3.6.3
AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity, priority and locking allowance configuration. The validity
depends on the results of input clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality Monitoring). Locking allowance is con-
figured by the corresponding INn_VALID bit(14
≥ n ≥ 1). Refer to
Figure 6. In all the qualified input clocks, the one with the highest priority
is
selected.
The
priority
is
set
by
the
corresponding
INn_SEL_PRIORITY[3:0] bits (14
≥ n ≥ 1). If more than one qualified
input clock INn is available and has the same priority, the input clock
with the smallest ‘n’ is selected.
Figure 6. Qualified Input Clocks for Automatic Selection
Table 9: Related Bit / Register in Chapter 3.6
Bit
Register
Address (Hex)
EXT_SW
MON_SW_PBO_CNFG
0B
T0_INPUT_SEL[3:0]
T0_INPUT_SEL_CNFG
50
T4_LOCK_T0
T4_INPUT_SEL_CNFG
51
T0_FOR_T4
T4_INPUT_SEL[3:0]
INn_SEL_PRIORITY[3:0] (14
≥ n ≥ 1)
IN1_IN2_SEL_PRIORITY_CNFG ~
IN13_IN14_SEL_PRIORITY_CNFG
26 ~ 2C *
INn_VALID (14
≥ n ≥ 1)
REMOTE_INPUT_VALID1_CNFG,
REMOTE_INPUT_VALID2_CNFG
4C, 4D
INn (14
≥ n ≥ 1)
INPUT_VALID1_STS, INPUT_VALID2_STS
4A, 4B
T4_T0_SEL
T4_T0_REG_SEL_CNFG
07
Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Validity
Priority
INn_SEL_PRIORITY[3:0]
'0000', (14 > n > 1)
Locking Allowance
INn_VALID = '0',
(14 > n > 1)
Yes
No
Yes
All qualified input clocks are available for Automatic selection
Input Clock Quality Monitoring
(LOS, Activity, Frequency)
INn = '1', (14 > n > 1)
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