參數(shù)資料
型號(hào)： IDTSSTE32882HLBAKG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 40/73頁
文件大?。?/td> 0K
描述： IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝： 170
類型： 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器
PLL： 是
主要目的： 存儲(chǔ)器，DDR3，RDIMM
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 5:60
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 1.282 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（13.5x8）
包裝： 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
45
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Power Down Mode Entry and Exit with IBT On
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882 into Register
Control Word access mode.
(3) UPon CKE Power Down exit, QxCSn will be held HIGH for a maximum of 1 tCK regardless of what DCSn input level is. For all other
operation, QxCSn outputs will follow DCSn inputs.
To re-enable the SSTE32882HLB from this Power Down Mode with IBT on, valid logic levels are required at all device inputs
when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High, the SSTE32882HLB
immediately starts driving High on the appropriate QxCKEn signals. The QxCSn signals are driven high and the QxODTn
signals follow the inputs. Other output signals QxRAS, QxCAS, QxWE and QxAddr are driven either high or low to ensure
stable valid logic on all device outputs when QxCKEn goes High. The device drives output signals to these levels for
tFIXEDOUTPUT to allow input receivers to be stablized. After the input receivers are stablized, the register output follow their
corresponding input levels. When exiting CKE power down mode, either one of the Chip Select register inputs DCSn can be
asserted for 1 tCK. For QuadCS capable register, when working in quad rank mode, either two of the Chip Select register
inputs DCSn can be asserted for 1 tCK. The device guarantees that input receivers are stablized within tFIXEDOUTPUT clocks
after DCKEn input is driven High. This is shown in the previous diagram.
CK
RESET
DAn,DBAn
DRAS,
DODTn
DCKEn
DCAS,
DWE
High, Low or Toggling
High or Low
Low
High
tInDIS
High
Hi-z
High
Yn
QxAn,
QxODTn
Follows Input (High, Low or Toggling)
Low
High
Hi-z
QxRAS,
QxCAS,
QxWE
QxCKEn
High or Low
Hi-z
tFixedoutput
Hi-z
tQDIS
Output buffers are Hi-z
n
n-1
n+4
n+8
n+12
n+16
n+20
n
n-1
n+4
n+8
n+12
n+16
n+20
QxBAn
DCS[j,1]
High or Low
High
Hi-z
High
Follows Input (High or Low)
Hi-z
High or Low
H or L
H, L or Hi-Z
H or L
Follows Input (High or Low)
tFixedoutput
High or Low
H, L or Hi-Z
High
H or L
PAR_IN
Hi-z
H, L or Hi-Z
DCS[i,0]
QxCS[j,1]
QxCS[i,0]
H, L or Hi-Z
H or L
Either or both DCKEn inputs are driven High
Either or both QxCKEn outputs are driven High
tEN
see Note 3
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IDTSSTE32882HLBBKG 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
IDTSSTE32882KA1AKG 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDTSSTE32882KA1AKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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