參數(shù)資料
型號(hào): IDTSSTE32882HLBAKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 67/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 170
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(13.5x8)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
7
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Ball Assignment: MIRROR = HIGH, QCSEN = HIGH or float
This table specifies the pinout for SSTE32882HLB in the back configuration (QuadCS mode disabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Also, balls Y10 and R6 are “do not use” balls reserved for DCS2
and DCS3 in the QuadCS mode, and must not be connected on the system. The device is designed to tolerate floating on these
pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas.
12
3
4
5
6
7
8
9
10
11
A
QAA13
QAA8
QCSEN
VSS
RESET
MIRROR
ERROUT
VSS
RSVD
QBA8
QBA13
B
QAA14
QAA7
QBA7
QBA14
C
QAA9
QAA6
VDD
QBA6
QBA9
D
QAA11
QAA5
VSS
QBA5
QBA11
E
QAA2
QAA4
VDD
QBA4
QBA2
F
QAA1
QAA3
VSS
QBA3
QBA1
G
QAA0
QABA1
VDD
QBBA1
QBA0
H
QAA12
QABA0
VSS
QBBA0
QBA12
J
QABA2
QACS1
VDD
QBCS1
QBBA2
K
QAA15
QACKE0
VSS
QBCKE0
QBA15
LQAWE
QACS0
VDD
QBCS0
QBWE
M
QAA10
QACKE1
VSS
QBCKE1
QBA10
N
QACAS
QAODT0
VDD
QBODT0 QBCAS
P
QARAS
QAODT1
DA4
VSS
DA3
QBODT1 QBRAS
R
DODT1
DA10
DA1
DA2
RSVD
DA5
DA15
DA14
DCKE1
T
DODT0
DCS1
DCS0
DCKE0
UDCAS
DA13
Y1
PVSS
VDD
PVDD
Y0
DBA2
DA12
VDWE
DRAS
Y1
PVSS
VSS
PVDD
Y0
DA11
DA9
W
DBA0
DA0
FBIN
Y3
AVSS
CK
RSVD
Y2
FBOUT
DA6
DA8
Y
DBA1
PAR_IN
FBIN
Y3
AVDD
CK
VREFCA
Y2
FBOUT
RSVD
DA7
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