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參數(shù)資料
| 型號(hào)： | IDTSSTE32882HLBAKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 49/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標(biāo)準(zhǔn)包裝： | 170 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（13.5x8） |
| 包裝： | 托盤 |
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
53
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
CONTROL WORDS
The SSTE32882HLB registers have internal control bits for adapting the configuration of certain device features. The control
bits are accessed by the simultaneous assertion of both DCS0 and DCS1 in the QuadCS disabled mode. In the QuadCS enabled
mode, the simultaneous assertion of both DCS2 and DCS3 during normal operation, and the assertion of all four DCS[3:0]
inputs also results in control word access. However, assertion of any three DCS[3:0] inputs is not legal. Register Qn outputs
including QxCKE0, QxCKE1, QxODT0 and QxODT1 remain in their previous state. Select signals QxCS[n:0] are set to high
during control word access.
The SSTE32882HLB allocates decoding for up to 16 words of control bits, RC0 through RC15. Selection of each word of
control bits is presented on inputs DA0 through DA2 and DBA2. Data to be written into the configuration registers need to be
presented on DA3, DA4, DBA0 and DBA1. Bits DA[15:5] need to be low, and at least one DCKEn input must be high, for
valid data access. If Power Down mode is enabled in RC9[DBA1], at least one DCKE must be high for valid control word
access. The inputs on DRAS, DCAS, DWE, and DODT[1:0] can be either high or low, and are ignored by the SSTE32882HLB
during control word access. In all cases Address and command parity is checked during control word write operations.
ERROUT is asserted and the command is ignored if a parity error is detected. Using this mechanism, controllers may use the
SSTE32882HLB to validate the address and command bus signal integrity to the module as long as one or more of the parity
checked input signals DA3-DA15, DBA0, DBA1, DRAS, DCAS, DWE are kept high.
Control word access must be possible at any defined frequency independent of the current setting of DBA1 control registers.
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| IDTSSTE32882HLBAKG8 | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTSSTE32882HLBBKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
| IDTSSTE32882KA1AKG | 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDTSSTE32882KA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA |
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