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參數(shù)資料
型號: IDTSSTE32882HLBAKG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 44/73頁
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標準包裝: 170
類型: 時鐘緩沖器/驅(qū)動器,多路復用器
PLL:
主要目的: 存儲器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應商設備封裝: 176-CABGA(13.5x8)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
49
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
DYNAMIC 1T/3T TIMING TRANSACTION AND OUTPUT INVERSION ENABLING/DISABLING
Output Inversion is always enabled by default, after RESET is de-asserted, to conserve power and reduce simultaneous output
switching current. All A-outputs will follow the equivalent inputs, however the following B-outputs will be driven to the
complement of the matching A-outputs: QBA3 - QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2.
The Output Inversion feature is not used during DRAM MRS command access. When Output Inversion is disabled, all
corresponding A and B output drivers of the SSTE32882HLB are driven to the same logic levels. Output Inversion must be
disabled when the MRS and EMRS commands must be issued to the DRAMs, for example, to assure that the same
programming is issued to all DRAMs in a rank.
With Output Inversion disabled during MRS access, in order to allow correct DRAM accesses with the consequently increased
simultaneous switching propagation delay the devices supports 3T timing. If this feature is invoked the device drives the
received data on its outputs for thee cycles instead of one. The only exceptions are the QxCS[n:0] outputs, which are the
QACS0, QACS1, QBCS0, and QBCS1 outputs in the QuadCS disabled mode and are QCS[3:0] in the QuadCS enabled mode.
When the device decodes the MRS command (DRAS=0, DCAS=0, DWE=0 and only one DCSn=0), it will disable the Output
Inversion function and pass the DRAM MRS command with an additional (one) clock delay on the appropriate QnCSx signal
to the DRAM. Back-to-back MRS command via the SSTE32882HLB must have a minimum of three clock delays. The
SSTE32882HLB will automatically enable Output Inversion if there is no DRAM MRS command three clocks after the
previous MRS command.
The inputs and outputs relationships for 1T timing and 3T timing are shown in the following three diagrams.
Output Inversion Functional Diagram
QAxxx output
QBxxx output
Dxxx input
MR
S
De
cod
er
Re
gi
st
er
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相關代理商/技術參數(shù)
參數(shù)描述
IDTSSTE32882HLBAKG8 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器,多路復用器 PLL:是 主要目的:存儲器,RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
IDTSSTE32882HLBBKG 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
IDTSSTE32882KA1AKG 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDTSSTE32882KA1AKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA