參數(shù)資料
型號: IS43R16800A1-5TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8Meg x 16 128-MBIT DDR SDRAM
中文描述: 8M X 16 DDR DRAM, 0.65 ns, PDSO66
封裝: LEAD FREE, PLASTIC, TSOP2-66
文件頁數(shù): 43/72頁
文件大小: 2174K
代理商: IS43R16800A1-5TL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/17/06
43
ISSI
IS43R16800A1
Truth Table 2: Clock Enable (CKE)
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
Current State
CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
1
Power Down
L
L
X
Maintain Power Down
Power Down
L
H
Deselect or NOP
Exit Power Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power Down Entry
All Banks Idle
H
L
Auto Refresh
Self Refresh Entry
Bank(s) Active
H
L
Deselect or NOP
Active Power Down Entry
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n (Same
Bank)”
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
XSNR
) period. A minimum of
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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IS43R16800A-6 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:8Meg x 16 128-MBIT DDR SDRAM