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參數(shù)資料
| 型號： | IS45S16100C1-7TLA |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO50 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50 |
| 文件頁數(shù)： | 34/81頁 |
| 文件大?。?/td> | 821K |
| 代理商： | IS45S16100C1-7TLA |
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IS45S16100C1
ISSI
34
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
01/03/06
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS45S16100C1 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IS45S16100C1 repeats the operation starting at the
256th cycle with data input returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
precharge command
must be executed within the ACT to PRE command
period (t
RAS
max.) following the burst stop command.
After the period (t
WBD
) required for burst data input to
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(t
WBD
) is zero clock cycles, regardless of the
CAS
latency.
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the
CAS
latency, two clock cycles (t
QMD
) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to the
HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time t
QMD
later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte output
(pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS
latency = 2, burstlength = 4
READ A0
COMMAND
UDQM
LDQM
DQ8-DQ15
DQ0-DQ 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
WRITE A0
COMMAND
DQ
CLK
D
IN
A0
D
IN
A1
D
IN
A
D
IN
A1
D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0)
BURST STOP
BST
PRE 0
INVALID DATA
PRECHARGE (BANK 0)
Don't Care
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PDF描述 |
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| IS45S16100C1-7TLA1 | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16400C1 | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16400C1-7TA1 | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16400C1-7TLA | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS45S16100C1-7TLA1 | 功能描述:動態(tài)隨機(jī)存取存儲器 16M (1Mx16) 143MHz Automotive Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS45S16100C1-7TLA1-TR | 功能描述:動態(tài)隨機(jī)存取存儲器 16M (1Mx16) 143MHz Automotive Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS45S16100E | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM |
| IS45S16100E-6TLA1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM |
| IS45S16100E-7BLA1 | 功能描述:動態(tài)隨機(jī)存取存儲器 16M (1Mx16) 143MHz S動態(tài)隨機(jī)存取存儲器 3.3v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
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