參數(shù)資料
型號: IS45S16100C1-7TLA
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO50
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50
文件頁數(shù): 7/81頁
文件大?。?/td> 821K
代理商: IS45S16100C1-7TLA
IS45S16100C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
01/03/06
7
AC CHARACTERISTICS
(1,2,3)
-7
Symbol Parameter
Min.
Max.
Units
t
CK
3
t
CK
2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
7
8
ns
ns
t
AC
3
t
AC
2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
5.5
6
ns
ns
t
CHI
CLK HIGH Level Width
2.5
ns
t
CL
CLK LOW Level Width
2.5
ns
t
OH
3
t
OH
2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2.0
2.5
ns
ns
t
LZ
Output LOW Impedance Time
0
ns
t
HZ
3
t
HZ
2
t
DS
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
2
5.5
6
ns
ns
ns
Input Data Setup Time
t
DH
Input Data Hold Time
1
ns
t
AS
Address Setup Time
2
ns
t
AH
Address Hold Time
1
ns
t
CKS
CKE Setup Time
2
ns
t
CKH
CKE Hold Time
1
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
2
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1
ns
t
RC
Command Period (REF to REF / ACT to ACT)
63
ns
t
RAS
Command Period (ACT to PRE)
42
100,000
ns
t
RP
Command Period (PRE to ACT)
20
ns
t
RCD
Active Command To Read / Write Command Delay Time
16
ns
t
RRD
Command Period (ACT [0] to ACT[1])
14
ns
t
DPL
3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
1CLK
ns
t
DPL
2
CAS
Latency = 2
1CLK
ns
t
DAL
3
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
CAS
Latency = 3
1CLK+t
RP
ns
t
DAL
2
CAS
Latency = 2
1CLK+t
RP
ns
t
T
Transition Time
1
10
ns
t
REF
Notes:
1. When power is first applied, memory operation should be started 100 μs after V
DD
and V
DDQ
reach their stipulated voltages. Also note that the
power-on
sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.) when the
output is in the high impedance state.
Refresh Cycle Time (4096)
64
ms
相關(guān)PDF資料
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IS45S16100C1-7TLA1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
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