參數(shù)資料
型號: ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 117/137頁
文件大小: 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
79 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
A DMA transfer is terminated when any of the following conditions are met:
The DMA count is complete
DMAEN = 0
The DMA controller asserts EOT.
When the DMA transfer is terminated, the buffer is also cleared (even if the data is not
completely read) and the DMA handler is disabled automatically. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
11.3 Endpoint descriptions
11.3.1
Endpoints with programmable FIFO size
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication ow between the host and the
device. At design time each endpoint is assigned a unique number (endpoint
identier, see Table 66). The combination of the device address (given by the host
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The DC has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 congurable
endpoints, which can be individually dened as interrupt/bulk/isochronous, IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either via
the Programmed I/O interface or via DMA.
11.3.2
Endpoint access
Table 66 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. DC FIFO DMA
access is selected and enabled via bits EPIDX[3:0] and DMAEN of the
DcDMAConguration register. A detailed description of the DC DMA operation is
given in Section 12.
[1]
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
[2]
The data ow direction is determined by bit EPDIR in the DcEndpointConguration register; see Section 13.1.1. IN: input for the USB
host (ISP1161A1 transmits); OUT: output from the USB host (ISP1161A1 receives).
11.3.3
Endpoint FIFO size
The size of the FIFO determines the maximum packet size that the hardware can
support for a given endpoint. Only enabled endpoints are allocated space in the
shared FIFO storage, disabled endpoints have zero bytes. Table 67 lists the
programmable FIFO sizes.
The following bits in the Endpoint Conguration register (ECR) affect FIFO allocation:
Endpoint enable bit (FIFOEN)
Table 66:
Endpoint access and programmability
Endpoint
identier
FIFO size[1]
(bytes)
Double
buffering
I/O mode
access
DMA mode
access
Endpoint type
0
64 (xed)
no
yes
no
control OUT[2]
0
64 (xed)
no
yes
no
control IN[2]
1 to 14
programmable
supported
programmable
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