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| 型號(hào)： | ISP1161A1BM,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64 |
| 文件頁(yè)數(shù)： | 69/137頁(yè) |
| 文件大?。?/td> | 599K |
| 代理商： | ISP1161A1BM,557 |
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Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
36 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
the end of the frame for full-speed and low-speed packets. By programming these
elds, the effective USB bus usage can be changed. Furthermore, the size of the ITL
buffers (HcITLBufferLength, 2AH to read, AAH to write) is programmed.
If a USB frame contains both ISO and AT packets, two interrupts will be generated
per frame.
One interrupt is issued concurrently with the SOF. This interrupt (bit ITLint is set in the
Hc
PInterrupt register) triggers reading and writing of the ITL buffer by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable ATL Interrupt (bit ATLint is set in the Hc
PInterrupt register)
is issued, which triggers reading and writing of the ATL buffer by the microprocessor,
after which the interrupt is cleared by the microprocessor. If the microprocessor
cannot handle the ISO interrupt before the next ISO interrupt, disrupted ISO trafc
can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, the Active bit and the TotalBytes eld are introduced (see Table 5).
Bit Active is cleared only if all data of the Philips Transfer Descriptor (PTD) has been
transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the
ATL are serviced, and the frame is not over yet, the HC starts looking for a PTD with
bit Active still set. If such a PTD is found and there is still enough time in this frame,
another transaction is started on the USB bus for this endpoint.
For ISO processing, the HCD also has to take care of the HcBufferStatus register
(2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data
into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depending on whether it
is ITL0 or ITL1) will be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM, the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must
be done within the 1 ms frame from which ITL0BufferDone or ITL1BufferDone was
set.
For example, the HCD writes ISO_A data into the ITL0 buffer in the rst frame. This
will cause the HcBufferStatus register to show that the ITL0 buffer is full by setting
bit ITL0BufferFull to logic 1. At this stage, the HCD cannot write ISO data into the
ITL0 buffer RAM again.
In the second frame, the HC will process the ISO_A data in the ITL0 buffer. At the
same time, the HCD can write ISO_B data into the ITL1 buffer. When the next SOF
comes (the beginning of the third frame), both ITL1BufferFull and ITL0BufferDone are
automatically set to logic 1.
In the third frame, the HCD has to read at least two bytes (one word) of the ITL0
buffer to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not
cleared, when the next SOF comes (the beginning of the fourth frame) the
ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also
applies to the ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To
recover from this state, a power-on reset or software reset will have to be applied.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161A1BMGA | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161A1BM-S | 功能描述:USB 接口集成電路 USB HOST+DEV CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BM-T | 功能描述:USB 接口集成電路 USB1.1 HOST/DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1161A1BMUM | 功能描述:IC USB HOST CONTROLLER 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1161ABD | 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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