參數(shù)資料
型號: ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 47/137頁
文件大?。?/td> 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
16 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.4 FIFO buffer RAM access by PIO mode
Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register elds. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
Figure 16 shows a complete access cycle of the HC internal FIFO buffer RAM. For a
write cycle, the microprocessor rst writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H to
read, A2H to write) is used to specify the byte count of a FIFO buffer RAM’s read
cycle or write cycle. Every access cycle must be in the same access direction. The
read cycle procedure is similar to the write cycle.
For access to the DC FIFO buffer RAM, see Section 13.
Fig 15. Accessing DC control registers.
A1, A0
WR
CS
11
10
MGT940
D[15:0]
RD
DC command
code
DC register data
(upper word)
DC register data
read
write
read
write
(lower word)
Fig 16. Internal FIFO buffer RAM access cycle.
MGT941
read/write data
#1 (16 bits)
FIFO buffer RAM access cycle (transfer counter = 2N)
t
read/write data
#2 (16 bits)
read/write data
#N (16 bits)
write command
(16 bits)
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