參數(shù)資料
型號： ISP1161A1BM,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 82/137頁
文件大?。?/td> 599K
代理商： ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
48 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.1.4
HcInterruptStatus register (R/W: 03H/83H)
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable
register (see Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear
individual bits in this register by writing logic 1 to the bit positions to be cleared, but
cannot set any of these bits. Conversely, the HC can set bits in this register, but
cannot clear the bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00H
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
HCR
Reset
00000000
Access
R/W
Table 13:
HcCommandStatus register: bit description
Bit
Symbol
Description
31 to 18
-
reserved
17 to 16
SOC[1:0]
SchedulingOverrunCount: The eld is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It will be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by HCD to monitor any persistent
scheduling problems.
15 to 1
-
reserved
0
HCR
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of
the HC, it moves to the USBSuspend state in which most of the
operational registers are reset, except those stated otherwise, and
no Host bus accesses are allowed. This bit is cleared by the HC
upon the completion of the reset operation. The reset operation
must be completed within 10
s. This bit, when set, does not
cause a reset to the Root Hub and no subsequent reset signaling
will be asserted to its downstream ports.
Table 14:
HcInterruptStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00H
Access
R/W
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161A1BMGA 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BM-S 功能描述:USB 接口集成電路 USB HOST+DEV CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BM-T 功能描述:USB 接口集成電路 USB1.1 HOST/DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BMUM 功能描述:IC USB HOST CONTROLLER 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161ABD 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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