參數(shù)資料
型號： ISP1161A1BM,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 44/137頁
文件大?。?/td> 599K
代理商： ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
13 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Figure 9 shows the DMA interface between a microprocessor system and the
ISP1161A1. The ISP1161A1 provides two DMA channels:
DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and the ISP1161A1 HC internal
FIFO buffer RAM.
DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer
between a microprocessor system memory and the ISP1161A1 DC internal FIFO
buffer RAM.
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the
ISP1161A1 provides an internal EOT signal to terminate the DMA transfer as well.
Setting the HcDMAConguration register (21H to read, A1H to write) enables the
ISP1161A1 HC internal DMA counter for DMA transfer. When the DMA counter
reaches the value set in the HcTransferCounter register (22H to read, A2H to write),
an internal EOT signal will be generated to terminate the DMA transfer.
8.3 Control register access by PIO mode
8.3.1
I/O port addressing
Table 3 shows the ISP1161A1 I/O port addressing. Complete decoding of the I/O port
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from the ISP1161A1 data
port. When WR is LOW, the microprocessor writes a command to the command port,
or writes data to the data port.
Fig 9.
DMA interface between a microprocessor and an ISP1161A1.
004aaa179
D[15:0]
RD
WR
DACK1
DREQ1
EOT
MICRO-
PROCESSOR
ISP1161A1
D[15:0]
P bus I/F
RD
WR
DACK1
DREQ1
DACK2
DREQ2
DACK2
DREQ2
EOT
Table 3:
I/O port addressing
Port
CS
A1,A0
(Bin)
Access
Data bus width
(bits)
Description
0
00
R/W
16
HC data port
1
0
01
W
16
HC command port
2
0
10
R/W
16
DC data port
3
0
11
W
16
DC command port
相關(guān)PDF資料
PDF描述
ISP1181BBS,551 UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
ISP1181BBS,518 UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
ISP1181BDGG,112 UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
ISP1183BS,157 UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
ISP1362EE,551 UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161A1BMGA 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BM-S 功能描述:USB 接口集成電路 USB HOST+DEV CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BM-T 功能描述:USB 接口集成電路 USB1.1 HOST/DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BMUM 功能描述:IC USB HOST CONTROLLER 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161ABD 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*