參數(shù)資料
型號(hào)： KM44S16020B
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 8M x 4Bit x 2 Banks Synchronous DRAM(8M x 4位 x 2組同步動(dòng)態(tài)RAM)
中文描述： 8米× 4位× 2銀行同步DRAM（8米× 4位× 2組同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 20/43頁
文件大?。?/td> 597K
代理商： KM44S16020B
CMOS SDRAM
DEVICE OPERATIONS - II
ELECTRONICS
REV. 3 Feb. '98
*Note :
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only the other bank precharge of dual banks operation.
5. Write Interrupted by Precharge & DQM
D
0
D
1
D
2
CLK
CMD
DQM
DQ
Masked by DQM
WR
PRE
D
3
Note 3
Note 2
6. Precharge
D
0
D
1
D
2
CLK
CMD
DQ
WR
PRE
D
3
1) Normal Write (BL=4)
tRDL
Note 2
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
PRE
Q
0
Q
1
Q
2
Q
3
Q
0
Q
1
Q
2
Q
3
1
2
*Note :
1. t
RDL
: Last data in to row precharge delay
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after t
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.
RP
from this point.
7. Auto Precharge
D
0
D
1
D
2
CLK
CMD
DQ
RD
D
3
1) Normal Write (BL=4)
Note 3
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
WR
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
Note 3
Auto Precharge Starts
相關(guān)PDF資料
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KM44S16020CT-G10 制造商:SEC 功能描述:
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KM44S32030B 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
KM44S32030BT-G/F10 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
KM44S32030BT-G/F8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
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