參數(shù)資料
型號: KSZ8841-PMQL
廠商: Micrel Inc
文件頁數(shù): 22/74頁
文件大?。?/td> 0K
描述: IC MAC CTRLR 32BIT 128-PQFP
應用說明: AN-142 Wake-on-LAN and Wake-Up Event
標準包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應商設備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱: 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
29
M9999-100407-1.5
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8841-PMQL. The following table shows the CFID register bit fields.
Bit
Default
Description
31 - 16
0x8841
Device ID
15 - 0
0x16C6
Vendor ID
Specifies the manufacturer of the KSZ8841-PMQL.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8841-PMQL’s ability to generate and respond to PCI cycles. When 0
is written to this register, the KSZ8841-PMQL logically disconnects from the PCI bus for all accesses except
configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
The following table describes the CFCS register bit fields.
Bit
Type
Default
Description
31
Status
0
Detected Parity Error
When set, indicates that the KSZ8841-PMQL detected a parity
error, even if parity error handling is disabled in parity error
response (CFCS[6]).
30
Status
0
Signal System Error
When set, indicates that the KSZ8841-PMQL asserted the system
error SERR_N pin.
29
Status
0
Received Master Abort
When set, indicates that the KSZ8841-PMQL terminated a master
transaction with master abort.
28
Status
0
Received Target Abort
When set, indicates that the KSZ8841-PMQL master transaction
was terminated due to a target abort.
27
Status
0
Target Abort
This bit is set by KSZ8841-PMQL whenever it terminates with a
Target Abort. The CSR registers are all 32-bit Little Endian format.
For PCI register Read cycles, the KSZ8841-PMQL allows any
different combination of CBEN. For PCI register bus cycles, only
byte, word (16-bit), or Dword (32-bit) accesses are allowed. Any
other combination is illegal and is target aborted.
26 - 25
Status
01
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a medium assertion of
DEVSEL_N.
Category
Description
Value after hardware reset
0x884116C6
Write access rules
Write has no effect on the KSZ8841-PMQL.
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