參數(shù)資料
型號(hào)： KSZ8841-PMQL
廠商： Micrel Inc
文件頁數(shù)： 45/74頁
文件大小： 0K
描述： IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說明： AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱： 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
5
M9999-100407-1.5
MAC DMA Transmit Start Command Register (MDTSC Offset 0x0008) ..................................................................... 38
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C) ..................................................................... 39
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)...................................................................... 39
Receive Descriptor List Base Address Register (RDLB Offset 0x0014) ...................................................................... 39
MAC Multicast Table 0 Register (MTR0 Offset 0x0020) .............................................................................................. 39
MAC Multicast Table 1 Register (MTR1 Offset 0x0024) .............................................................................................. 40
Interrupt Enable Register (INTEN Offset 0x0028) ........................................................................................................ 40
Interrupt Status Register (INTST Offset 0x002C)......................................................................................................... 41
MAC Additional Station Address Low Register (MAAL0-15) ........................................................................................ 42
MAC Additional Station Address High Register (MAAH0-15)....................................................................................... 42
MAC/PHY and Control Registers ................................................................................................................................... 43
MAC Address Register Low (0x0200): MARL .............................................................................................................. 43
MAC Address Register Middle (0x0202): MARM ......................................................................................................... 44
MAC Address Register High (0x0204): MARH............................................................................................................. 44
On-Chip Bus Control Register (Offset 0x0210): OBCR................................................................................................ 44
EEPROM Control Register (Offset 0x0212): EEPCR................................................................................................... 44
Memory BIST Info Register (Offset 0x0214): MBIR ..................................................................................................... 45
Global Reset Register (Offset 0x0216): GRR............................................................................................................... 45
Power Management Capabilities Register (Offset 0x0218): PMCR............................................................................. 46
Wakeup Frame Control Register (Offset 0x021A): WFCR ........................................................................................... 47
Wakeup Frame 0 CRC0 Register (Offset 0x0220): WF0CRC0.................................................................................... 48
Wakeup Frame 0 CRC1 Register (Offset 0x0222): WF0CRC1.................................................................................... 48
Wakeup Frame 0 Byte Mask 0 Register (Offset 0x0224): WF0BM0............................................................................ 48
Wakeup Frame 0 Byte Mask 1 Register (Offset 0x0226): WF0BM1............................................................................ 48
Wakeup Frame 0 Byte Mask 2 Register (Offset 0x0228): WF0BM2............................................................................ 48
Wakeup Frame 0 Byte Mask 3 Register (Offset 0x022A): WF0BM3 ........................................................................... 49
Wakeup Frame 1 CRC0 Register (Offset 0x0230): WF1CRC0.................................................................................... 49
Wakeup Frame 1 CRC1 Register (Offset 0x0232): WF1CRC1.................................................................................... 49
Wakeup Frame 1 Byte Mask 0 Register (Offset 0x0234): WF1BM0............................................................................ 49
Wakeup Frame 1 Byte Mask 1 Register (Offset 0x0236): WF1BM1............................................................................ 49
Wakeup Frame 1 Byte Mask 2 Register (Offset 0x0238): WF1BM2............................................................................ 50
Wakeup Frame 1 Byte Mask 3 Register (Offset 0x023A): WF1BM3 ........................................................................... 50
Wakeup Frame 2 CRC0 Register (Offset 0x0240): WF2CRC0.................................................................................... 50
Wakeup Frame 2 CRC1 Register (Offset 0x0242): WF2CRC1.................................................................................... 50
Wakeup Frame 2 Byte Mask 0 Register (Offset 0x0244): WF2BM0............................................................................ 50
Wakeup Frame 2 Byte Mask 1 Register (Offset 0x0246): WF2BM1............................................................................ 51
Wakeup Frame 2 Byte Mask 2 Register (Offset 0x0248): WF2BM2............................................................................ 51
Wakeup Frame 2 Byte Mask 3 Register (Offset 0x024A): WF2BM3 ........................................................................... 51
Wakeup Frame 3 CRC0 Register (Offset 0x0250): WF3CRC0.................................................................................... 51
Wakeup Frame 3 CRC1 Register (Offset 0x0252): WF3CRC1.................................................................................... 51
Wakeup Frame 3 Byte Mask 0 Register (Offset 0x0254): WF3BM0............................................................................ 52
Wakeup Frame 3 Byte Mask 1 Register (Offset 0x0256): WF3BM1............................................................................ 52
Wakeup Frame 3 Byte Mask 2 Register (Offset 0x0258): WF3BM2............................................................................ 52
Wakeup Frame 3 Byte Mask 3 Register (Offset 0x025A): WF3BM3 ........................................................................... 52
Chip ID and Enable Register (Offset 0x0400): CIDER ................................................................................................. 52
Chip Global Control Register (Offset 0x040A): CGCR ................................................................................................. 53
Indirect Access Control Register (Offset 0x04A0): IACR ............................................................................................. 53
Indirect Access Data Register 1 (Offset 0x04A2): IADR1 ............................................................................................ 54
Indirect Access Data Register 2 (Offset 0x04A4): IADR2 ............................................................................................ 54
Indirect Access Data Register 3 (Offset 0x04A6): IADR3 ............................................................................................ 54
Indirect Access Data Register 4 (Offset 0x04A8): IADR4 ............................................................................................ 54
Indirect Access Data Register 5 (Offset 0x04AA): IADR5 ............................................................................................ 54
Reserved (Offset 0x04C0-0x04CF) .............................................................................................................................. 54
PHY 1 MII Register Basic Control Register (Offset 0x04D0): P1MBCR ...................................................................... 55
PHY 1 MII Register Basic Status Register (Offset 0x04D2): P1MBSR ........................................................................ 56
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