參數(shù)資料
型號： KSZ8841-PMQL
廠商： Micrel Inc
文件頁數(shù)： 3/74頁
文件大?。?/td> 0K
描述： IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說明： AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱： 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
11
M9999-100407-1.5
Pin
Number
Pin
Name
Type
Pin Function
45
RXP1
I/O
Physical receive (MDI) or transmit (MDIX)signal (+ differential)
46
RXM1
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential)
47
AGND
Gnd
Analog ground
48
TXP1
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential)
49
TXM1
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
NC
—
No connect
53
NC
—
No connect
54
AGND
Gnd
Analog ground
55
NC
—
No connect
56
NC
—
No connect
57
VDDA
P
1.2 analog VDD
58
AGND
Gnd
Analog ground
59
NC
—
No connect
60
NC
—
No connect
61
ISET
O
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
Gnd
Analog ground
63
VDDAP
P
1.2V analog VDD for PLL
64
AGND
Gnd
Analog ground
65
X1
I
66
X2
O
25MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is no connected.
Note: Clock is
50ppm for both crystal and oscillator.
67
RSTN
Ipu
Hardware Reset, Active Low
RSTN will cause the KSZ8841-PMQL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
68
PAR
I/O
PCI Parity
Even parity computed for PAD[31:0] and CBE[3:0]N, master drives PAR for address
and write data phase, target drives PAR for read data phase.
69
FRAMEN
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction in a bus master mode. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed to it.
70
IRDYN
I/O
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD[31:0]
during write data phases, indicates it is ready to accept data during read data phases.
As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on
the bus.
71
TRDYN
I/O
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD[31:0]
during read data phases, indicates it is ready to accept data during write data phases.
As a master, it will monitor this TRDYN signal that indicates the target is ready for data
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8841-PMQL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 KSZ8841-PMQL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8841-PMQLI 功能描述:以太網(wǎng) IC Single Ethernet Port + 32-bit/33MHz PCI interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with PCI Interface
KSZ8842-16 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
KSZ8842-16_08 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2-Port Ethernet Switch with Non-PCI Interface
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