參數(shù)資料
型號(hào): KSZ8841-PMQL
廠商: Micrel Inc
文件頁(yè)數(shù): 29/74頁(yè)
文件大小: 0K
描述: IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說(shuō)明: AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝: 66
控制器類(lèi)型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱(chēng): 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
35
M9999-100407-1.5
Power-Management Control and Status Register (CPMC Offset 54H)
The CMPC register is a power-management control and status register. This register can control and sate power
management events. The following table shows the CMPC register bit fields.
Bit
Default
Description
31 - 16
0x0000
Reserved
15
0
PME_Status
This bit indicates that the KSZ8841-PMQL has detected a power-
management event. If bit PME_Enable is set, the KSZ8841-PMQL also
asserts the PME_N pin. This bit is cleared on power-up reset or by write
1. It is not modified by either hardware or software reset. When this bit is
cleared, the KSZ8841-PMQL deserts the PME_N pin.
14 - 9
0x00
Reserved
8
0
PME_Enable
If this bit is set, the KSZ8841-PMQL can assert the PME_N pin.
Otherwise, assertion of the PME_N pin is disabled. This bit is cleared on
power-up reset only and is not modified by either hardware or software
reset.
7 - 4
0x0
Reserved
3
0
No Soft Reset
If this bit is set (“1”), the KSZ8841-PMQL does not perform an internal
reset when transitioning from D3_hot to D0 because of PowerState
commands. Configuration context is preserved. Upon transition from
D3_hot to the D0 Initialized state, no additional operating system
intervention is required to preserve configuration context beyond writing
the PowerState bits.
If this bit is cleared (“0”), the KSZ8841-PMQL does perform an internal
reset when transitioning from D3_hot to D0 via software control of the
PowerState bits. Configuration context is lost when performing the soft
reset. Upon transition from D3_hot to the D0 state, full reinitialization
sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by a
system or bus segment reset will return to the device state D0
Uninitialized with only PME context preserved if PME is supported and
enabled.
2
0
Reserved
1 - 0
00
Power State
This field is used to set the current power state of the KSZ8841-PMQL
and to determine its power state. The definitions of the field values are:
0: D0
1: D1
2: D2
3: D3(hot)
This field gets a value of 0 after power up.
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