參數(shù)資料
型號: KSZ8841-PMQL
廠商: Micrel Inc
文件頁數(shù): 50/74頁
文件大?。?/td> 0K
描述: IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說明: AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱: 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
54
M9999-100407-1.5
Indirect Access Data Register 1 (Offset 0x04A2): IADR1
This register contains the indirect data for the chip function.
Bit
Default
R/W
Description
15-8
0x00
RO
Reserved
7
0
RO
CPU Read Status
Only for dynamic and statistics counter reads.
1 = Read is still in progress
0 = Read has completed
6-3
0x0
RO
Reserved
2-0
000
RO
Reserved
Indirect Access Data Register 2 (Offset 0x04A4): IADR2
This register contains the indirect data for the chip function.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect data
Bit 47-32 of indirect data
Indirect Access Data Register 3 (Offset 0x04A6): IADR3
This register contains the indirect data for the chip function.
Bit
Default
R/W
Description
15-0
0x0000
RW
Reserved
Indirect Access Data Register 4 (Offset 0x04A8): IADR4
This register contains the indirect data for the chip function.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect data
Bit 15-0 of indirect data
Indirect Access Data Register 5 (Offset 0x04AA): IADR5
This register contains the indirect data for the chip function.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect data
Bit 31-16 of indirect data
Reserved (Offset 0x04C0-0x04CF)
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