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參數(shù)資料
| 型號： | KSZ8842-PMBL AM TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 42/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SW 2PORT 100LFBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | PCI |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 100-LFBGA |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
29
M9999-100207-1.5
Broadcast Storm Protection
The KSZ8842-PMQL/PMBL has an intelligent option to protect the switch system from receiving too many broadcast
packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch
resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8842-PMQL/PMBL has the
option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally,
and can be enabled or disabled on a per port basis in P1CR1[7] and P2CR1[7]. The rate is based on a 67ms interval
for 100Base-T and a 670ms interval for 10Base-T. At the beginning of each interval, the counter is cleared to zero and
the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in
SGCR3[15:18]. The default setting is 0x63 (99 decimal). This is equal to a rate of 1% minimum size packets, calculated
as follows:
148,800 frames/sec X 67 ms/interval X 1% = 99 frames/interval (approx.) = 0x63
Where 148,800 frames/sec is based on 64-byte blocks of 100Base-T packets with 12 bytes of IPG and 8 bytes of
preamble between packets.
Repeater Mode
When KSZ8842-PMQL/PMBL is set to repeater mode (SGCR3[7] = 1), it only works on 100BT half-duplex mode. In
repeater enabled mode, all ingress packets will broadcast to other two ports without MAC check and learning. Before
setting the device to repeater mode, the user has to set bit 13 (100Mbps), bit 12 (auto-negotiation disabled) and bit 8
(half duplex) in both P1MBCR and P2MBCR registers as well as to set bit 6 (host half duplex) in SGCR3 register for
repeater mode.
The latency in repeater mode is defined from the 1st bit of DA into the ingress port 1 to the 1st bit of DA out of the
egress port 2. The minimum is 270 ns and the maximum is 310 ns (one clock skew of 25 MHz between TX and RX).
Clock Generator
The X1 and X2 pin/balls are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz
oscillator (as described in the pin/ball description). The PCI Bus Interface supports a maximum speed of 33MHz PCLK
(PCI Bus Clock).
Advanced Switch Functions
Spanning Tree Support
To support spanning tree, the host port is the designated port for the processor.
The other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and
“l(fā)earning disable” register settings in registers P1CR2 and P2CR2 for ports 1 and 2, respectively. Table 4 shows the
port setting and software actions taken for each of the five spanning tree states.
Disable State
Port Setting
Software Action
The port should
not forward or
receive any
packets. Learning
is disabled.
“transmit enable = 0,
receive enable = 0,
learning disable = 1”
The processor should not send any packets to the port. The switch
may still send specific packets to the processor (packets that
match some entries in the “static MAC table” with “overriding bit”
set) and the processor should discard those packets. Address
learning is disabled on the port in this state.
Blocking State
Port Setting
Software Action
Only packets to
the processor are
forwarded.
“transmit enable = 0,
receive enable = 0,
learning disable = 1”
The processor should not send any packets to the port(s) in this
state. The processor should program the “Static MAC table” with
the entries that it needs to receive (for example, BPDU packets).
The “overriding” bit should also be set so that the switch will
forward those specific packets to the processor. Address learning
is disabled on the port in this state.
Listening State
Port Setting
Software Action
Only packets to
and from the
processor are
“transmit enable = 0,
receive enable = 0,
learning disable = 1”
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets). The
“overriding” bit should be set so that the switch will forward those
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| KSZ8851-16MLLI TR | IC MAC CTLR 1PORT W/BUS 48LQFP |
| KSZ8851-16MLLJ | IC CTLR MAC 1PORT NON-PCI 48LQFP |
| KSZ8851-32MQLI | IC CTLR MAC/PHY NON PCI 128PQFP |
| KSZ8851-32MQL | IC CTLR MAC/PHY NON PCI 128PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8842-PMBL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 2+1 Port 10/100 Ethernet Switch with 32b/33MHz PCI Interface (BGA Version) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8842-PMBL-TR | 功能描述:Ethernet Switch 10/100 Base-T/TX PHY PCI Interface 100-LFBGA (9x9) 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):停產(chǎn) 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:PCI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:3.1 V ~ 3.5 V 電流 - 電源:122mA 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LFBGA 供應(yīng)商器件封裝:100-LFBGA（9x9） 標(biāo)準(zhǔn)包裝:1 |
| KSZ8842-PMQL | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8842-PMQL-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 KSZ8842-PMQL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| KSZ8842-PMQLI | 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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