參數(shù)資料
型號: KSZ8842-PMBL AM TR
廠商: Micrel Inc
文件頁數(shù): 53/119頁
文件大小: 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
39
M9999-100207-1.5
The following table shows the TDES3 register bit fields.
Bit
Description
31 - 0
Next Descriptor Address
Indicates the physical memory address of the next descriptor in the descriptor ring.
The buffer address must be Word aligned.
PCI Configuration Registers
The KSZ8842-PMQL/PMBL implements 12 configuration registers. These registers are described in the following
subsections.
The KSZ8842-PMQL/PMBL enables a full software-driven initialization and configuration. This allows the software to
identify and query the KSZ8842-PMQL/PMBL. The KSZ8842-PMQL/PMBL treats configuration space write operations
to registers that are reserved as no-ops. That is, the access completes normally on the bus and the data is discarded.
Read accesses, to reserved or unimplemented registers, complete normally and a data value of 0 is returned.
Software reset has no effect on the configuration registers. Hardware reset sets the configuration registers to their
default values.
Configuration Register
Identifier
I/O Address Offset
Default
Identification
CFID
00H
0x884116C6
Command and Status
CFCS
04H
0x02000000
Revision
CFRV
08H
0x02000010
Latency Timer
CFLT
0CH
0x00000000
Base Memory Address
CBMA
10H
0x00000000
Reserved
14H-28H
0x00000000
Subsystem ID
CSID
2CH
0x********
Reserved
38H
0x00000000
Interrupt
CFIT
3CH
0x28140100
Reserved
40H-4CH
0x00000000
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8842-PMQL/PMBL. The following table shows the CFID register bit fields.
Bit
Default
Description
31 - 16
0x8842
Device ID
15 - 0
0x16C6
Vendor ID
Specifies the manufacturer of the KSZ8842-PMQL/PMBL.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8842-PMQL/PMBL’s ability to generate and respond to PCI cycles.
When 0 is written to this register, the KSZ8842-PMQL/PMBL logically disconnects from the PCI bus for all accesses
except configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
Category
Description
Value after hardware reset
0x884216C6
Write access rules
Write has no effect on the KSZ8842-PMQL/PMBL.
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