參數資料
型號: KSZ8842-PMBL AM TR
廠商: Micrel Inc
文件頁數: 91/119頁
文件大小: 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標準包裝: 1,000
控制器類型: 以太網開關控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應商設備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
73
M9999-100207-1.5
PHY2 LinkMD Control/Status (Offset 0x04F4): P2VCT
This register contains the LinkMD control and status of PHY 2:
Bit
Default
R/W
Description
Is the same as:
15
0 (Self_Clear)
RW
Vct_enable
1 = the cable diagnostic test is enabled. It’ll be self-
cleared after VCT test is done
0 = it indicates the cable diagnostic test is
completed and the status information is valid for
read
P2SCSLMD, bit 12
14:13
0
RO
Vct_result
[00] = normal condition
[01] = open condition has been detected in cable
[10] = short condition has been detected in cable
[11] = cable diagnostic test is failed
P2SCSLMD, bits
14-13
12
RO
Vct 10M short
1 = Less than 10 meter short
P2SCSLMD, bit 15
11 – 9
0
RO
Reserved
8 – 0
0
RO
Vct_fault_count
Distance to the fault. The distance is approximately
0.4m X vct_fault_count
P2SCSLMD, bits 8-
0
PHY2 Special Control/Status Register (Offset 0x04F6): P2PHYCTRL
This register contains the control and status information of PHY2:
Bit
Default
R/W
Description
Is the same as:
15 – 6
0
RO
Reserved
5
0
RO
Polarity reverse (polrvs)
1 = polarity is reversed
0 = polarity is not reversed
P2SR, bit 13
4
0
RO
MDIX Status (mdix_st)
1 = MDI
0 = MDIX
P2SR, bit 7
3
0
RW
Force Link (force_lnk)
1 = force link pass
0 = normal operation
P2SCSLMD, bit 11
2
1
RW
Power Saving (pwrsave)
1 = Disable
0 = Enable power saving
P2SCSLMD, bit 10
1
0
RW
Remote loop back (near end loop back )
1 = Loop back at PMD/PMA of port 2’s PHY
0 = normal operation.
P2SCSLMD, bit 9
0
RW
Reserved
Reserved (Offset 0x04F8 - 0x04FA)
Bit
Default
R/W
Description
15 – 0
0x0000
RO
Reserved
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