參數(shù)資料
型號: KSZ8842-PMBL AM TR
廠商: Micrel Inc
文件頁數(shù): 81/119頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
64
M9999-100207-1.5
Indirect Access Control Register (Offset 0x04A0): IACR
This register contains the indirect control for the switch function.
Bit
Default
R/W
Description
15 – 13
000
RW
Reserved
12
0
RW
Read High. Write Low
1 = read cycle
0 = write cycle
11:10
00
RW
Table select
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic address table selected
11 = MIB counter selected
9 – 0
0x000
RW
Indirect address
Bit 9-0 of indirect address
Note: (1) write IACR will actually trigger a command.
Read or write access is determined by Register bit 12.
Indirect Access Data Register 1 (Offset 0x04A2): IADR1
This register contains the indirect data for the switch function.
Bit
Default
R/W
Description
15 – 8
0x000
RO
Reserved
7
0
RO
CPU Read Status
Only for dynamic and statistics counter reads.
1 = read is still in progress
0 = read has completed
6 – 3
0x0
RO
Reserved
2 – 0
000
RO
Indirect data.
Bit 66-64 of indirect data
Indirect Access Data Register 2 (Offset 0x04A4): IADR2
This register contains the indirect data for the switch function.
Bit
Default
R/W
Description
15 – 0
0x0000
RW
Indirect data
Bit 47-32 of indirect data
Indirect Access Data Register 3 (Offset 0x04A6): IADR3
This register contains the indirect data for the switch function.
Bit
Default
R/W
Description
15 – 0
0x0000
RW
Indirect data
Bit 63-48 of indirect data
Indirect Access Data Register 4 (Offset 0x04A8): IADR4
This register contains the indirect data for the switch function.
Bit
Default
R/W
Description
15 – 0
0x0000
RW
Indirect data
Bit 15-0 of indirect data
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