參數(shù)資料
型號(hào)： LAN9116
廠商： SMSC Corporation
英文描述： Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述： 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù)： 112/126頁
文件大?。?/td> 831K
代理商： LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
112
SMSC LAN9116
DATASHEET
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
Table 6.2
also shows the number of dummy reads that are
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note:
Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
Note:
The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Table 6.2 Read After Read Timing Rules
AFTER
READING...
WAIT FOR THIS MANY
NS…
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING TCYC OF
165NS)
BEFORE READING...
RX Data FIFO
495
3
RX_FIFO_INF
RX Status FIFO
495
3
RX_FIFO_INF
TX Status FIFO
495
3
TX_FIFO_INF
RX_DROP
660
4
RX_DROP
Figure 6.1 LAN9116 PIO Read Cycle Timing
Data Bus
nCS, nRD
A[7:1]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAN9116-MD 功能描述:以太網(wǎng) IC Efficient Sngl Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9116-MT 功能描述:以太網(wǎng) IC Ethernet IC 32bit Superior Perf RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9117 制造商:SMSC 制造商全稱:SMSC 功能描述:HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9117-MD 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9117-MT 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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