參數(shù)資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 95/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
95
Revision 1.1 (05-17-05)
DATASHEET
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address
0x06 of the EEPROM. Please refer to
Section 4.6
for more information on the EEPROM. Section
5.4.3
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the
Ethernet physical address.
5.4.3
ADDRL—MAC Address Low Register
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from
address 0x04 of the EEPROM. Please refer to
Section 4.6
for more information on the EEPROM.
Table 5.7
below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and ADDRL and ADDRH registers.
BITS
DESCRIPTION
31-16
Reserved
15-0
Physical Address [47:32].
This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9116 device. The content of this field is undefined until loaded from the EEPROM at power-
on. The host can update the contents of this field after the initialization process has completed.
Offset:
3
Attribute:
R/W
Default Value:
FFFFFFFFh
Size:
32 bits
BITS
DESCRIPTION
31-0
Physical Address [31:0].
This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9116 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering
EEPROM ADDRESS
ADDRN
ORDER OF RECEPTION ON
ETHERNET
0x01
ADDRL[7:0]
1
st
0x02
ADDRL[15:8]
2
nd
0x03
ADDRL[23:16]
3
rd
0x04
ADDRL[31:24]
4
th
0x05
ADDRH[7:0]
5
th
0x06
ADDRH[15:8]
6
th
相關PDF資料
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