參數(shù)資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 15/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
15
Revision 1.1 (05-17-05)
DATASHEET
Table 2.1 Host Bus Interface Signals
PIN NO.
NAME
SYMBOL
BUFFER
TYPE
#
PINS
DESCRIPTION
21-26,29-
33,36-40
Host Data High
D[31:16]
I/O8 (PD)
16
Bi-directional data port. Supports
Big/Little Endian Byte ordering.
Note that Pull-down’s are disabled in
32 bit mode.
43-46,49-
53,56-59,62-
64
Host Data Low
D[15:0]
I/O8
16
Bi-directional data port. Supports
Big/Little Endian Byte ordering.
12-18
Host Address
A[7:1]
IS
7
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
92
Read Strobe
nRD
IS
1
Active low strobe to indicate a read
cycle.
93
Write Strobe
nWR
IS
1
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9116
when it is in a reduced power state.
94
Chip Select
nCS
IS
1
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9116 when it is in a
reduced power state.
72
Interrupt
Request
IRQ
O8/OD8
1
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
71,73,75,84,
90,91
Reserved
Reserved
5
No Connect
74
10/100
Selector
SPEED_SEL
I (PU)
1
This signal functions as a configuration
input on power-up and is used to select
the default Ethernet settings. Upon
deassertion of reset, the value of the
input is latched. This signal functions
as shown in
Table 2.2, "Default
Ethernet Settings"
, below.
76
FIFO Select
FIFO_SEL
IS
1
When driven high all accesses to the
LAN9116 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
SPEED_SEL
SPEED
DUPLEX
AUTO NEG.
0
10MBPS
HALF-DUPLEX
DISABLED
1
100MBPS
HALF-DUPLEX
ENABLED
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