參數(shù)資料
型號: LAN9116
廠商: SMSC Corporation
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 高效的單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 86/126頁
文件大?。?/td> 831K
代理商: LAN9116
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
86
SMSC LAN9116
DATASHEET
5.3.20
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
This register is used to control the read and write operations with the MAC CSR’s
5.3.21
MAC_CSR_DATA – MAC CSR Synchronizer Data Register
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write
operations with the MAC CSR’s
Offset:
A4h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
CSR Busy.
When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
SC
0
30
R/nW.
When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
R/W
0
29-8
Reserved.
RO
-
7-0
CSR Address.
The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
R/W
00h
Offset:
A8h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-0
MAC CSR Data.
Value read from or written to the MAC CSR’s.
R/W
00000000h
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