參數(shù)資料
型號： LC72715PW
廠商： SANYO SEMICONDUCTOR CO LTD
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁數(shù)： 10/26頁
文件大?。?/td> 167K
代理商： LC72715PW
LC72715PW
No.A1650-18/26
(2) Read registers
List of read registers
ADR
R/W
Register Name
Description
0h
R
PDATO
Input this address into A0 to A3 after reading of error-corrected data
1h
R
STAT
Status register
2h
R
BLNO
Block number register
3h and beyond
-
Reserved
Parallel mode: To read registers, send address shown in the list of read registers.
CCB mode: To read registers, send assigned CCB address (FBh or FDh). It is not necessary to send address shown in
the list of read registers.
1h <STAT>: Status register <Read Only>
Register to confirm various states
ADR
Register Name
Bit
Name
Description
Reset
7
VH
Determination on vertically error corrected data
0: Data for which only horizontal correction is performed
1: Data for which vertical and second horizontal correction after horizontal correction
are performed
0
6
BLK
Block synchronization state
0: Data that is received when block synchronization is not established
1: Data that is received when block synchronization is established
0
5
FRM
Frame synchronization state
0: Data that is received when frame synchronization is not established
1: Data that is received when frame synchronization is established
0
4
ERR
Error correction state
0: Data whose correction is completed and for which error is not detected by the layer 2
CRC check
1: Data whose correction is impossible or for which error is detected by the layer 2 CRC
check.
0
3
PRI
Determination of parity block
0: Data that is estimated to be data block by the frame synchronization circuit
1: Data that is estimated to be parity block by the frame synchronization circuit
0
2
HEAD
Frame head determination
1: Data that is estimated to be the frame head block by the frame synchronization circuit
0: Data other than above
0
1
CRC4
Layer 4 CRC check result
0: Error in layer 4 CRC check result
1: No error in layer 4 CRC check result
1
1h
STAT
0
-
Reserved
0
2h <BLNO>: Block Number register <Read Only>
Register to confirm the output data block Number
ADR
Register Name
Bit
Name
Description
Reset
7
BLN7
0
6
BLN6
0
5
BLN5
0
4
BLN4
0
3
BLN3
0
2
BLN2
0
1
BLN1
0
2h
BLNO
0
BLN0
Indicates the block Number or parity block Number of output data
Data block Number
0 to 189
Parity block Number
0 to 81
0
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