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參數(shù)資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大小： | 167K |
| 代理商： | LC72715PW |
LC72715PW
No.A1650-10/26
Symbol
Parameter
min
typ
max
unit
tCL
Clock “L” level time
0.7
μs
tCH
Clock “H” level time
0.7
μs
tSU
Data setup time
0.7
μs
tHD
Data hold time
0.7
μs
tEL
CE wait time
0.7
μs
tES
CE setup time
0.7
μs
tEH
CE hold time
0.7
μs
tLC
Data latch change time
0.7
μs
O
tDD
*1
O
D
data output time
277
555
ns
2
O
tDD
O
D
data output off time
140
ns
tCRC
CRC4 change period
0.7
μs
*1 DO data output change time from the “H” level to the “L” level. Output change time from the “L” level to the “H”
level is determined by the external pull-up resistance value and load capacitance value.
CPU Interface <Parallel Mode>
This LSI can perform control via the parallel interface, in addition to the CCB interface. To use the parallel interface, it
is necessary to set the SP pin = L. The data bus width can be selected with the BUSWD pin. (BUSWD pin - L: 8 bits,
H: 16 bits)
The DMA transmission method can also be selected according to the setting of control register.
(1) Data input (register setting)
Data is set to the register in LSI. For accessing, input the register address to A0 to A3 pins and the write data to the
D(n) pin.
Set the CS pin = L, and then the WR pin = L. Subsequently, by setting the WR pin = H and the CS pin = H after the
tWWRL period, the data can be set to the register. It is necessary to keep an interval of tCYWR or more before the
next data input.
tSAWR
tWDH
tWWRL
tCYWR
A0 to A3
CS
WR
D(n)
tHAWR
tWDS
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