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參數(shù)資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 167K |
| 代理商： | LC72715PW |
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LC72715PW
No.A1650-8/26
CPU Interface <CCB Mode>
CCB (Computer Control Bus), which is the Sanyo original serial bus format for Sanyo’s acoustic LSIs, performs data
input and output.
The CCB address is transmitted with CE= “L”, acknowledging the CCB I/O mode when CE is set to “H”.
(1) List of CCB modes
CCB address
Hexadecimal
B0
B1
B2
B3
A0
A1
A2
A3
I/O mode
Description
FAh
0
1
0
1
Input
16-bit control data input
FBh
1
0
1
Output
Output of data corresponding to the
input clock (CL) portion
FCh
0
1
Input
Layer 4 CRC check circuit data input
(on the 8-bit units)
FDh
1
0
1
Output
Output of the register only
(2) Data input (CCB address FAh)
This is to set data to the LSI internal register. DI input includes both CCB address FAh and 16-bit data (DI0 to
DI15) are input.
Assignment of each bit is as shown in the table below. Though DI12 to DI15 are invalid data, it is necessary to enter
the arbitrary data so that the total of 16 bits can be obtained. For the contents of each register and register address,
refer to the chapter of CPU registers.
(Note that writing into the layer 4 CRC check register will be described later (for the CCB address, use FCh.))
(3) Output of the corrected data (CCB address FBh)
The corrected packet data is output from LSI. The CCB address, FBh, is input in DI.
The valid data to be output is maximum 288 bits. If the clock input (CL input) is interrupted halfway to set CE to the
“L” level, data output is not troubled by the next interrupt.
The maximum data to be output is 288 bits (36 bytes) and the leading two bytes, to which the status register
(STAT) contents and the block number register (BLNO) contents are added, are output.
STAT and BLNO, which are the register contents outputs, are output respectively with LSB first.
The corrected data is output sequentially beginning with the leading bit in data of one block.
The BIC code is not output.
In case of data reading for multiple times by one interrupt signal (INT), the output data is not guaranteed.
STAT (8)
BLN0 (8)
Data block (176)
Error-corrected data
Layer 2 CRC (14)
Parity (82)
7
O
D
to
0
O
D
15
O
D
to
8
O
D
16
O
D
to
191
O
D
205
O
D
to
192
O
D
287
O
D
to
206
O
D
(LSB)
Input data (8-bit)
(MSB)
Register address
Invalid data
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12 to DI15
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT0
BIT1
BIT2
BIT3
BIT4 to BIT7
DI0
B0
B1
B2
B3
A0
A1
A2
A3
DI1
DI13
DI14
DI15
tCH
tCL
CE
CL
DI
Internal data latch
tSU
tHD
tEL
tES
tLC
tEH
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