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參數(shù)資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 167K |
| 代理商： | LC72715PW |
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LC72715PW
No.A1650-16/26
4h <CTL1>: Control register 1 <Write Only>
Register to control the block reset ON/OFF, function activation/stop, and the data output method.
ADR
Register Name
Bit
Name
Description
Reset
7
CRC4_RST
Layer 4 CRC check circuit reset setting
1: Reset ON
0: Reset OFF
To cancel reset, it is necessary to set 0.
0
6
O
D
_MOVE
Sets the
O
D
pin output method changeover
0: Hi-Z state retained in states other than data output
1: Changes in an interlocked manner with the INT signal
0
5
INT_MOVE
Sets changeover of corrected data output method *4
0: Outputs only data received at completion of correction & layer 2 CRC
completion as well as during synchronization
1: Outputs all of data
0
4
SYNC_RST
Synchronization regeneration circuit reset setting *1
1: Reset ON
0: Reset OFF
0 to be set to cancel reset
0
3
EC_STOP
Error correction function down setting *2
0: All functions activated
1: Only MSK detector circuit and synchronization regeneration circuit activated
0
2
VEC_HALT
Vertical error correction function down function *3
0: Executes vertical error correction and second horizontal correction.
1: Does not execute vertical error correction and second horizontal correction.
0
1
-
Reserved
0
4h
CTL1
0
-
Reserved
0
*1 With SYNC_RST=1, the synchronization status and the synchronization protection status are cleared, resulting in the
unsynchronized state. This function enables rapid pull-in of frame synchronization when the frame synchronization
of new tuned and received data is deviated during tuning of a radio receiver. In this case, registers such as the
number of allowable BIC errors, the number of block forward/backward protections, and the number of frame
forward/backward protections are not initialized. During reset, the INT signal is not output and the DO pin becomes
the HI-Z output.
*2 With EC_STOP=1, all of operations and data output related to error correction is shut down. MSK demodulation,
synchronization circuits, serial data input, and layer 4 CRC circuit remain operative.
*3 With VEC_HALT=1 setting, all of LSI operation related to vertical correction and second horizontal correction are
shut down. Only the data after first horizontal correction is output.
*4 Since the output mode will be modified depending on the setting of the VEC_OUT flag or the result of horizontal
error correction, refer to the “List of operation modes” section for detail.
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