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參數(shù)資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 167K |
| 代理商： | LC72715PW |
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LC72715PW
No.A1650-22/26
(3) Horizontally-corrected Data Output Timing (Relationship With The Received Data)
The timing relationship between the received data and interrupt control signal (INT) for horizontary-corrected data
output is shown. But the delay from the actual received signal caused by demodulation in the MSK demodulation block
is ignored.
Block synchronization is established by determining the BIC code. Data of the Nth packet can be output during
receiving of the next (N + 1) packet data.
(4) Vertically-corrected Data Output Timing
Vertical correction is made when the data of one frame is stored in the memory, frame synchronization has been
established, and when horizontal correction cannot correct all of packet data. Vertical correction start timing is the head
of a frame. During receiving of the first to 28
th packets of the N-th frame, horizontal correction of each packet is made,
transferring data to the CPU interface. Using the idling time in this period, vertical correction of the previous (N-1)-th
frame data is made.
Vertically-corrected data is output for the amount equivalent to 190 blocks sequentially beginning with reception of the
29
th packet (block), in such a manner that one block data is output each time one block is received. Only data of data
block in the FM multiplex broadcasting frame is output.
The final 190
th block is output during reception of the 218th block.
In the vertically-corrected data output timing, the packet data corrected by horizontal correction is not output (INT not
issued). However, vertical correction data output order is not shortened for the amount equivalent to the packet data that
is not output. For example, if the first to 100
th data packets have been horizontally corrected, the 101st vertically
corrected packet data is output, not at the reception point of the block Number 29
th, but at the 129th packet data
reception point.
(N-1) packet
N packet
(N+1) packet
Received data
(N-1) packet data output period
Period during which data cannot be guaranteed
N packet data output period
BIC
18ms
300ns max
62.5
μs
300ns max
1ms
BCK
INT
68
μs
Data output period after
vertical correction of
previous frame
Reception block No.
N-th frame
(N-1)-th frame
271
272
1
2
3
28
29
30
31
218
219
220
18ms
1ms
12
189
190
BCK
FCK
INT
18ms
9ms
18ms
×28=504ms
62.5
μs
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